1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the adjustment of characteristics of individual field effect transistor elements so as to enhance the performance thereof.
2. Description of the Related Art
Integrated circuits typically include a large number of individual circuit elements, such as transistors, capacitors, resistors and the like. For enhancing overall performance of the integrated circuit, usually the number of individual circuit elements is increased, thereby implementing more and more functions into the circuit, and associated therewith the feature sizes of the individual circuit elements are reduced, thereby enhancing performance of the individual circuit elements, in particular of the transistors, which represent the dominant components in complex circuits. Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, MOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed, manufacturing costs and/or power consumption. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed in and on an appropriate semiconductor material, wherein currently the vast majority of logic circuitry is fabricated on the basis of silicon. Typically, a MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a channel region disposed between the drain region and the source region, wherein the channel region is weakly doped with respect to the drain and source regions. The conductivity of the channel region, which represents an essential device criterion, as the reduced current drive capability of scaled devices with reduced transistor width has, at least partially, to be compensated for by an increased conductivity, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a transistor width, the distance between the source and drain regions, which is also referred to as channel length. In addition to the conductivity of the channel region in the saturated state and the linear operating state of the transistor, performance is also significantly influenced by the transistor's capability of rapidly creating a conductive channel in the channel region upon application of a specified control voltage to the gate electrode, since usually the transistors are operated in a switched mode requiring a fast transition from the transistor on-state to the transistor off-state and vice versa. Moreover, other aspects also have to be taken into consideration when designing a transistor of high performance circuits. For instance, static and dynamic leakage currents may significantly affect the overall performance of an integrated circuit, as the achievable amount of heat dissipation that is required for transistor architectures producing high dynamic and/or static leakage currents may restrict the maximum practical operating frequency.
Furthermore, sophisticated lateral and vertical dopant profiles may be required in the drain and source regions so as to maintain controllability of the channel region for a channel length of approximately 50 nm and significantly less, as is typically applied in modern transistor elements. As is well known, short channel effects may require a reduction of the thickness of the gate insulation layer which, however, may no longer be a viable option on the basis of silicon dioxide since, at a thickness of approximately 1 nm, significant leakage currents may occur, as explained above. Appropriate design countermeasures on the other hand may be accompanied by a reduction of channel conductivity, which has resulted in advanced strain engineering techniques for creating a desired type of strain in the channel region which may enhance charge carrier mobility therein. For example, for a standard crystallographic orientation of a silicon layer, i.e., a (100) surface orientation with the channel length directed along a <110> crystal axis, creating a tensile strain along the channel length direction may significantly enhance electron mobility, which thus leads to increased drive current capability of an NMOS transistor.
Similarly, a compressive strain in the channel region of P-channel transistors for a standard crystallographic configuration may result in a superior mobility of holes, thereby also enhancing overall transistor performance of P-channel transistors. One mechanism that is frequently applied in sophisticated P-channel transistors is the incorporation of a silicon/germanium alloy in the drain and source areas, which may be grown in corresponding cavities on the basis of epitaxial growth techniques, thereby achieving a strained state which in turn may act on the adjacent channel region, thereby inducing the required type of strain therein.
Moreover, as discussed above, upon further scaling the overall transistor dimensions, the gate electrode structures may be appropriately adapted so as to provide the required controllability of the channel region. Since a further reduction of the thickness of well-established silicon dioxide-based gate dielectric materials may be less than desirable due to the significant increase of leakage currents, the capacitive coupling between the gate electrode and the channel region is frequently increased by providing a high-k dielectric material in sophisticated gate electrode structures. Generally, a high-k dielectric material may be understood hereinafter as a dielectric material having a dielectric constant of 10.0 and higher, as determined by well-established measurement techniques. For example, a plurality of compounds including metals, such as hafnium, zirconium, aluminum and the like, may be used as high-k dielectric materials. Furthermore, since an appropriate work function of the electrode material of any such sophisticated gate electrode structures may no longer be obtained on the basis of doped polysilicon material and due to polysilicon's characteristic to form a depletion zone in the vicinity of the gate dielectric material upon operating the transistor, a metal-containing electrode material is typically formed above the high-k dielectric material. To this end, appropriate metal species have to be incorporated, such as lanthanum, aluminum and the like, possibly in combination with appropriate carrier materials, such as tantalum, tantalum nitride, titanium nitride and the like. In some sophisticated approaches for providing high-k metal gate electrode structures, the high-k dielectric material and the associated work function metal species and electrode material may be provided in an early manufacturing stage, wherein additionally a well-established electrode material, such as silicon, may be used in combination with a work function adjusting electrode material, thereby providing a certain degree of compatibility with conventional gate electrode structures. Since typically, in complex semiconductor devices, transistors of different threshold voltage may have to be applied, thereby requiring highly complex dopant profiles in the channel region and the adjacent drain and source regions, it may be increasingly difficult to comply with these requirements on the basis of sophisticated gate electrode structures, even if different work function metal species may be provided, for instance for P-channel transistors and N-channel transistors, respectively. For example, in some cases, it may be advantageous to incorporate a semiconductor material of appropriately designed electronic characteristics in order to obtain the desired threshold voltage in combination with sophisticated high-k metal gate electrode structures. To this end, frequently silicon/germanium may be provided in the channel region of P-channel transistors so as to obtain a pronounced offset of the band gaps of P-channel transistors and N-channel transistors, since a silicon/germanium alloy has a reduced band gap compared to the silicon base material. Consequently, a plurality of process techniques have been developed based on the technical experience obtained for processing silicon and germanium materials in order to appropriately incorporate a silicon/germanium alloy, for instance in the channel region and/or in drain and source areas for providing appropriately adapted electronic characteristics and/or specific strain conditions, in particular in P-channel transistors.
Although the incorporation of silicon/germanium alloys in sophisticated transistors may provide superior performance, in particular for P-channel transistors comprising a high-k metal gate electrode structure, a further reduction of the critical dimensions, for instance the gate length of planar transistors to 40 nm and less, may not be associated with a corresponding increase of overall transistor performance without implementing additional performance enhancing mechanisms, which may specifically relate to an increase of charge carrier mobility in the channel regions of the transistors. For example, it has been proposed to incorporate materials selectively in the silicon base material, which are known to have a higher intrinsic charge carrier mobility compared to silicon, silicon/germanium and the like. It turns out, however, that the incorporation of any such materials is associated with a high risk of device failures since many process steps and integration aspects are still completely unknown in the field of forming sophisticated silicon-based semiconductor devices. Moreover, the electronic characteristics of these materials may result in lower gate capacitance, reduced inversion layer density and thus reduced drive current compared to silicon/germanium materials.
In view of the situation described above, the present disclosure relates to semiconductor devices and manufacturing techniques in which sophisticated transistor elements may be provided with superior performance, while avoiding or at least reducing one or more of the problems identified above.